Hardware In The Loop Wiki

Under construction

These notes are being tightened as final screenshots, measurements, and layout callouts are added.

Purpose

The Hardware-in-the-Loop platform reproduces the electrical behavior of flight sensors, actuators, power rails, and communication interfaces so avionics hardware can be tested without a complete vehicle.

The point is repeatability. It can test fault conditions, sensor trajectories, actuator commands, and electrical interfaces that would otherwise require hazardous or expensive vehicle-level equipment.

My Responsibility

I designed major analog, power, and interface sections of the schematic, selected components, and built circuit simulations for the programmable sensor and actuator-emulation paths.

Architecture

The board combines:

The architecture separates the control software from the electrical interface layer. The CM5 commands DACs and switches, while analog circuitry turns those commands into the voltage, current, or resistance behavior expected by the flight hardware.

Sensor Emulation

Different sensors need fundamentally different emulation methods.

Voltage-output and differential sensors can be reproduced using DACs and precision amplifier stages. Current-loop sensors require controlled current generation. RTDs require programmable resistance behavior. Thermocouples require low-level differential voltages with careful offset and noise control.

Each channel should eventually be documented with:

Power Architecture

The platform includes multiple switching and linear regulators to provide vehicle-like and logic-level voltage domains. Power conversion must support representative loads without allowing converter noise to contaminate low-level sensor emulation.

Power-stage layouts should make the switching loops, bulk capacitance, current return paths, thermal spreading, and separation from low-noise analog circuitry easy to see.

Control and Communications

The CM5 provides the high-level test interface. Ethernet, USB, CAN, SPI, and GPIO support control, data logging, and hardware-interface emulation.

This lets automated tests command a stimulus, observe the hardware response, compare it against expected behavior, and save a reproducible test record.

Validation Plan

  1. Bring up every power rail independently.
  2. Verify CM5 boot and communication.
  3. Exercise ADC channels with precision references.
  4. Verify DAC outputs unloaded.
  5. Validate each amplifier and sensor-emulation transfer function.
  6. Test current-loop compliance across representative loads.
  7. Check RTD and thermocouple emulation against calibrated instrumentation.
  8. Exercise valve and deployment interfaces with safe loads.
  9. Measure channel noise and crosstalk.
  10. Run automated end-to-end tests against representative flight hardware.

Current Status

The schematic architecture is substantially developed, while PCB layout and physical validation remain in progress. The portfolio should clearly separate calculated, simulated, and measured results as the project advances.

Next Revision

Add per-channel calibration storage, clearer analog-ground partitioning documentation, automated self-test loops, and a standardized connector scheme for rapidly swapping flight-hardware configurations.